The field of the present invention pertains to the field of electronic design automation. More particularly, the present invention pertains to test and floorplanning equivalent processes within the field of electronic design automation of integrated circuit devices.
The rapid growth of the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist and automate most steps of the circuit design process. Typical circuits today contain hundreds of thousands or millions of individual pieces or xe2x80x9ccells.xe2x80x9d Such a design is much too large for a circuit designer or even an engineering team of designers to manage effectively manually. To automate the circuit design and fabrication of integrated circuit devices, electronic design automation (EDA) systems have been developed.
An EDA system is a computer software system designers use for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this high level design language description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. The generic netlist can be translated by the EDA system into a lower level technology-specific netlist based on a technology-specific library that has gate-specific models for timing and power estimation. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. The netlist is then used to generate a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
As ASICs and other complex integrated circuits have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as the number of gates and transistors increase, the time which an ASIC spends in testing increases as well. This increase incurs an additional cost on ASIC manufacturing. The testing cost can be very significant for the latest and largest ASIC designs. In addition, as more complex systems-on-a-chip devices proliferate, which, for example, integrate complex logic units (integer units, floating point units, memory, etc.) into a single chip, and as newly-designed processors begin to take advantage of the ability to integrate large quantities of memory on-chip, it has become necessary to increase the comprehensiveness, efficiency, and accuracy of the design checking and testing schemes utilized to ensure proper operation of these devices (e.g., ASICs, complex integrated circuits, field programmable gate arrays, etc.).
Thus, an increasingly important part of the logic synthesis process involves designing for testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. One approach to DFT is to take the netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of applying test vectors is called stimulation of the design, and the special memory cells and associated circuitry are referred to as DFT implementations. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. On the other hand, issues concerning observability deal with facilitating the capturing the output of the circuitry.
The portions of an integrated circuit that are Designed to perform its intended or expected operational function are called its xe2x80x9cmission modexe2x80x9d circuitry, while the portions added to the integrated circuit to facilitate testability are called xe2x80x9ctest modexe2x80x9d circuitry or DFT implementations. The resultant circuit, therefore, has two functional modes, mission and test.
An exemplary flow chart diagram of a typical design automation process, including a DFT process, is shown in FIG. 1. The process 100 described with respect to this flow chart is implemented within a computer system in a CAD environment. Within the process 100, a circuit designer first generates a high-level description 105 of a circuit in a hardware description language such as VHDL or Verilog. The high-level description 105 is then converted into a netlist 115 by using a computer implemented synthesis process 110 such as the xe2x80x9cDesign Compilerxe2x80x9d by Synopsys, Inc., of Mountain View, Calif. A netlist 115 is a description of the electronic circuit which specifies what cells compose the circuit and which pins of which cells are to be connected together using interconnects (xe2x80x9cnetsxe2x80x9d). At this point the netlist 115 consists of xe2x80x9cmission modexe2x80x9d circuitry.
At block 120, a constraint-driven scan insertion process is performed to implement testability cells or xe2x80x9ctest modexe2x80x9d cells into the overall integrated circuit design. In this process 120, memory cells of the netlist 115 are replaced with scannable memory cells that are specially designed to apply and observe test vectors or patterns to and from portions of the integrated circuit. In addition, process 120 performs linking groups of scannable memory cells (xe2x80x9cscan cellsxe2x80x9d) into scan chains so that the test vectors can be cycled into and out of the integrated circuit design. The output of the scan insertion process 120 is a scannable netlist 125 that contains both xe2x80x9cmission modexe2x80x9d and xe2x80x9ctest modexe2x80x9d circuitry.
The scannable netlist 125, however, does not contain any information with respect to the physical design of the circuit. For example, the netlist 125 does not specify where the cells are placed on a circuit board or silicon chip, or where the interconnects run. Determining this physical design information is the function of a computer controlled layout process 130.
The layout process 130 first finds a location for each cell on a circuit board or silicon chip. The locations are typically selected to optimize certain objectives such as wire length, circuit speed, power consumption, and/or other criteria, arid subject to the condition that the cells are spread evenly over the circuit board or silicon chip and that the cells do not overlap with each other. The layout process 130 also generates the wire geometry based on the placement information for connecting the pins of the cells together. The output of the automatic cell layout process 130 includes cell placement data structures and wire geometry data structures 135 that are used to make the final geometric database needed for fabrication of the circuit.
The layout of a typical design is not influenced by the test mode logic. Therefore, the layout process 130 in some cases may break up the scan chains and place the scan cells in such a way that the layout of the mission mode circuitry is not affected. The layout process 130 then reconnects the scan chain based on the placement of the scan cells. This process is also known as placement-based scan chain re-ordering.
Placement-based scan chain re-ordering works well in single clock domains, but does not work well in modem IC designs that have multiple clock domains or sequential elements that trigger on different clock edges (e.g., that have different edge sensitivities). Complications arise when a particular order is picked by the constraint-driven scan insertion process 120 and the layout process 130 violates the essence of this order. For example, scan insertion process 120 may configure a scan chain such that negative-edge triggered scan cells precede positive-edge triggered scan cells. In this case, placement-based scan chain re-ordering may mix memory cells with different clock edges, resulting in incorrect functionality of the circuit.
Accordingly, there exists a need for a process and system for placing and routing the test mode logic without significant impact to the layout of mission mode circuitry. What is also needed is a process and system for constructing scan chains that is not purely based on placement of the functional logic. What is yet further needed is a process and system for re-ordering scan cells that does not nullify ordering limitations predefined by DFT processes. The present invention provides these advantages and others not recited above but described in the following.
A computer implemented process and system are described for providing layout planning for test mode circuitry of an integrated circuit design. The present invention provides a floorplanning equivalent for test to take care of the link between test and layout to improve integrated circuit designs. The present invention feeds forward detailed information to the layout process to improve the ordering of scan cells that are determined during the layout process.
The novel process includes the steps of partitioning a scan chain into sets of re-orderable scan cells, and providing data representative of the sets of re-orderable scan cells to layout processes, e.g., placement and routing processes, as re-ordering limitations. Particularly, the re-ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set. In this manner, important test information can be forwarded to the layout processes to maintain selected scan cell orderings.
According to one embodiment of the present invention, the partitioning process divides the scan-chain into a number of sets based on clock domain information. If the scan chain includes lock-up latches, each set is further partitioned into a plurality of subsets based on the position of the lock-up latches. If the scan chain includes reconfigurable multiplexers, each subset containing reconfigurable multiplexer is further partitioned into smaller subsets based on the location of the reconfigurable multiplexer. In the present embodiment, the partitioning process may further divide the scan chain based on surrounding cone logic and SSO (Simultaneous Switching Outputs) requirements. Data representative of the resulting sets are then provided to the layout processes, e.g., place-and-route processes, to be used as re-ordering limitations.
Embodiments of the present invention include the above and further include an electronic design automation system comprising a logic synthesis system for receiving a HDL description of an integrated circuit design and for generating a scannable netlist based on the HDL description, wherein the logic synthesis process comprises a scan-insertion process for inserting a scan chain in the integrated circuit design; a scan chain partitioning system for partitioning the scan chain into a plurality of sets of re-orderable scan cells; and a place-and-route system for generating a layout from the scannable netlist, wherein the place-and-route system re-orders the scan chain to reduce routing congestion by only rearranging re-orderable scan cells within their respective sets.
Thus, by allowing the re-ordering of scan cells within only respective sets, the present invention provides for a method of placing and routing test mode logic that makes use of important test information to thereby reduce the impact of test mode logic on the layout of mission mode circuitry. In addition, any ordering limitations predefined by DFT processes will also be recognized by the present invention, and will be applied during placing and routing of the test mode logic. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.